vishay siliconix si9110, si9111 document number: 70004 s11-0975-rev. i, 16-may-11 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 high-voltage switchmode controllers features ? 10 v to 120 v input range ? current-mode control ? high-speed, source-sink output drive ? high efficiency operation (> 80 %) ? internal start-up circuit ? internal oscillator (1 mhz) ? shutdown and reset ? reference selection si9110 - 1 % si9111 - 10 % description the si9110/9111 are bic/dmos integrated circuits designed for use as high-performance switchmode controllers. a high-voltage dmos input allows the controller to work over a wide range of input voltages (10 to 120 vdc). current-mode pwm control circuitry is implemented in cmos to reduce internal power consumption to less than 10 mw. a push-pull output driver prov ides high-speed switching for mospower devices large enough to supply 50 w of output power. when combined with an output mosfet and transformer, the si9110/911 1 can be used to implement single-ended power converter topologies (i.e., flyback, forward, and cuk). the si9110/9111 are available in both standard and lead (pb)-free 14-pin plastic dip and soic packages which are specified to operate over the industrial temperature range of - 40 c to 85 c. functional block diagram + - + + - + - + - fb comp discharge osc 14 13 9 8 7 2 v ref gen r s q r s q sense 3 5 4 11 12 current-mode comparator c/l 1.2 v undervoltage reset 8.1 v 8.6 v bias current sources to internal circuits 10 1 6 2 comparator error amplifier v ref v cc +v in v cc shutdown 4 v osc out osc in - v in pre-regulator/start-up output to v cc comparator clock ( 1 / 2 f osc ) -
www.vishay.com 2 document number: 70004 s11-0975-rev. i, 16-may-11 vishay siliconix si9110, si9111 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. device mounted with all leads soldered or welded to pc board. b. derate 6 mw/c above 25 c. c. derate 7.2 mw/c above 25 c. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings parameter limit unit voltages referenced to - v in (note: v cc < + v in + 0.3 v) v cc 15 v +v in 120 logic inputs (reset, shutdown , osc in, osc out) - 0.3 to v cc + 0.3 linear inputs (feedback, sense, bias, v ref ) - 0.3 to v cc + 0.3 hv pre-regulator input current (continuous) 5 ma storage temperature - 65 to 150 c operating temperature - 40 to 85 junction temperature (t j ) 150 power dissipation (package) a 14-pin plastic dip (j suffix) b 750 mw 14-pin soic (y suffix) c 900 thermal impedance ( ? ja ) 14-pin plastic dip 167 c/w 14-pin soic 140 recommended operating range parameter limit unit voltages referenced to - v in v cc 9.5 to 13.5 v + v in 10 to 120 f osc 40 khz ? to 1 mhz r osc 25 k ?? to 1 m ? linear inputs 0 to v cc - 3 v digital inputs 0 to v cc specifications a parameter symbol test conditions unless otherwise specified discharge = - v in = 0 v v cc = 10 v, + v in = 48 v r bias = 390 k ? , r osc = 330 k ? d suffix - 40 c to 85 c unit temp. b min. d typ. c max. d reference output voltage v r osc in = - v in (osc disabled) r l = 10 m ? si9110 room 3.92 4.0 4.08 v si9111 room 3.60 4.0 4.40 si9110 full 3.86 4.14 si9111 full 3.52 4.46 output impedance e z out room 15 30 45 k ? short circuit current i sref v ref = - v in room 70 100 130 a temperature stability e t ref full 0.5 1.0 mv/c oscillator maximum frequency e f max r osc = 0 room 1 3 mhz initial accuracy f osc r osc = 330 k, see note f room 80 100 120 khz r osc = 150 k, see note f room 160 200 240 voltage stability ? f/f ? f/f = f(13.5 v) - f(9.5 v)/f(9.5 v) room 10 15 % temperature coefficient e t osc full 200 500 ppm/c
document number: 70004 s11-0975-rev. i, 16-may-11 www.vishay.com 3 vishay siliconix si9110, si9111 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. refer to process option flowchart for additional information. b. room = 25 c, full = as determined by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimu m and the most positive a maximum. e. guaranteed by design, no t subject to production test. f. c stray pin 8 = ? 5 pf. specifications a parameter symbol test conditions unless otherwise specified discharge = - v in = 0 v v cc = 10 v, + v in = 48 v r bias = 390 k ? , r osc = 330 k ? d suffix - 40 c to 85 c unit temp. b min. d typ. c max. d error amplifier feedback input voltage v fb fb tied to comp osc in = - v in , (osc disabled) si9110 room 3.96 4.00 4.04 v si9111 room 3.60 4.00 4.40 input bias current i fb osc in = - v in , v fb = 4 v room 25 500 na input offset voltage v os osc in = - v in (osc disabled) room 15 40 mv open loop voltage gain e a vol room 60 80 db unity gain bandwidth e bw room 1 1.3 mhz dynamic output impedance e z out room 1000 2000 ? output current i out source (v fb = 3.4 v) room - 2.0 - 1.4 ma sink (v fb = 4.5 v) room 0.12 0.15 power supply rejection psrr 9.5 v ? v cc ? 13.5 v room 50 70 db current limit threshold voltage v source v fb = 0 room 1.0 1.2 1.4 v delay to output e t d v sense = 1.5 v, see figure 1 room 100 150 ns pre-regulator/start-up input voltage + v in i in = 10 a room 120 v input leakage current + i in v cc ? 9.4 v room 10 a pre-regulator start-up current i start pulse width ? 300 s, v cc = v ulvo room 8 15 ma v cc pre-regulator turn-off threshold voltage v reg i pre-regulator = 10 a room 7.8 8.6 9.4 v undervoltage lockout v uvlo room 7.0 8.1 8.9 v reg - v uvlo v delta room 0.3 0.6 supply supply current i cc v load ? 75 pf (pin 4) room 0.45 0.6 1.0 ma bias current i bias room 10 15 20 a logic shutdown delay e t sd c l = 500 pf, v sense = - v in , see figure 2 room 50 100 ns shutdown pulse width e t sw see figure 3 room 50 reset pulse width e t rw room 50 latching pulse width shutdown and reset low e t lw see figure 3 room 25 input low voltage v il room 2.0 v input high voltage v ih room 8.0 input current input voltage high i ih v in = 10 v room 1 5 a input current input voltage low i il v in = 0 v room - 35 - 25 output output high voltage v oh i out = - 10 ma room full 9.7 9.5 v output low voltage v ol i out = 10 ma room full 0.30 0.50 output resistance r out i out = 10 ma, source or sink room full 20 25 30 50 ? rise time e t r c l = 500 pf room 40 75 ns fall time e t f room 40 75
www.vishay.com 4 document number: 70004 s11-0975-rev. i, 16-may-11 vishay siliconix si9110, si9111 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 timing waveforms typical characteristics figure 1. 90 % output sense 1.5 v - 50 % 0 t d t r 10 ns v cc 0 - figure 2. 90 % output 0 - 50 % t f 10 ns v cc v cc t sd shutdown 0 - 0 - 50 % 50 % 50 % 50 % reset 0 - v cc v cc t sw t lw t rw shutdown t r , t f 10 ns 50 % t v cc = - v in +v (v) 140 120 100 80 60 40 20 0 10 15 20 +i in (ma) in figure 5. output switching frequency vs. oscillator resistance (hz) 1 m 10 k 100 k 10 k 100 k 1 m f out r osc ( )
document number: 70004 s11-0975-rev. i, 16-may-11 www.vishay.com 5 vishay siliconix si9110, si9111 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pin configurations and ordering information detailed description pre-regulator/start-up section due to the low quiescent current requirement of the si9110/ 9111 control circuitry, bias power can be supplied from the unregulated input power source, from an external regulated low-voltage supply, or from an auxiliary "bootstrap" winding on the output inductor or transformer. when power is first applied during start-up, + v in (pin 2) will draw a constant current. the magnitude of this current is determined by a high-volta ge depletion mosfet device which is connected between + v in and v cc (pin 6). this start-up circuitry provides initial power to the ic by charging an external bypass capacitance connected to the v cc pin. the constant current is disabled when v cc exceeds 8.6 v. if v cc is not forced to exceed the 8.6 v threshold, then v cc will be regulated to a nominal value of 8.6 v by the pre-regulator circuit. as the supply voltage rises toward the normal operating conditions, an internal undervoltage (uv) lockout circuit keeps the output driver disabled until v cc exceeds the undervoltage lockout threshol d (typically 8.1 v). this guarantees that the control logic will be functioning properly and that sufficient gate drive voltage is available before the mosfet turns on. the design of the ic is such that the undervoltage lockout threshold will be at least 300 mv less than the pre-regulator turn-off voltage. power dissipation can be minimized by providing an external power source to v cc such that the constant curre nt source is always disabled. note: during start-up or when v cc drops below 8.6 v the start-up circuit is capable of sourcing up to 20 ma. this may lead to a high level of power dissipation in the ic (for a 48 v input, approximately 1 w). exce ssive start-up time caused by external loading of the v cc supply can result in device damage. figure 6 gives the typi cal pre-regulator current at bic/dmos as a function of input voltage. bias to properly set the bias for the si9110/9111, a 390 k ? resistor should be tied from bias (pin 1) to - v in (pin 5). this determines the magnitude of bias current in all of the analog sections and the pull-up current for the shudown and reset pins. the current flowin g in the bias resistor is nominally 15 a. reference section the reference section of the si9110 consists of a temperature compensated buried zener and trimmable divider network. the output of the reference section is connected internally to the n on-inverting input of the error amplifier. nominal reference output voltage is 4 v. the trimming procedure that is used on the si9110 brings the output of the error amplifier (whi ch is configured for unity gain during trimming) to within 1 % of 4 v. this compensates for input offset voltage in the error amplifier. the output impedance of the reference section has been purposely made high so that a low impedance external voltage source can be used to override the internal voltage source, if desired, without otherwise altering the performance of the device. applications which use a separ ate external reference, such as non-isolated converter topol ogies and circuits employing optical coupling in the feedback loop, do not require a trimmed voltage reference with 1 % accuracy. the si9111 accommodates the requirements of these applications at a lower cost, by leaving the reference voltage untrimmed. the 10 % accurate reference thus provided is sufficient to establish a dc bias point for the error amplifier. error amplifier closed-loop regulation is provided by the error amplifier, which is intended for use with "around-the-amplifier" compensation. a mos differential input stage provides for low input current. the noninverting input to the error amplifier (v ref ) is internally connected to the output of the reference supply and should be bypassed with a small capacitor to ground. bias fb +v in comp sense reset output shutdown -v in v ref v cc discharge osc out osc in dual-in-line and soic 1 2 3 4 5 6 7 14 13 12 11 10 9 8 top view ordering information part number temperature range package si9110dy - 40 c to 85 c soic-14 si9110dy-t1 si9110dy-t1-e3 SI9111DY SI9111DY-t1 SI9111DY-t1-e3 si9110dj pdip-14 si9110dj-e3 si9111dj si9111dj-e3
www.vishay.com 6 document number: 70004 s11-0975-rev. i, 16-may-11 vishay siliconix si9110, si9111 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 detailed description (cont?d) oscillator section the oscillator consists of a ring of cmos inverters, capacitors, and a capacitor discharge switch. frequency is set by an external resistor between the osc in and osc out pins. (see figure 5 for details of resistor value vs. frequency.) the discharge pin should be tied to - v in for normal internal oscillator operation. a frequency divider in the logic section limits switch duty cycle to ? 50 % by locking the switching frequency to one half of the oscillator frequency. remote synchronization is accomplished by capacitive coupling of a positive sync pulse into the osc in (pin 8) terminal. for a 5 v pulse amplitude and 0.5 s pulse width, typical values would be 100 pf in series with 3 k ? to pin 8. shutdown and reset shutdown (pin 11) and reset (pin 12) are intended for overriding the output mosfet switch via external control logic. the two inputs are fed through a latch preceding the output switch. d epending on th e logic state of reset, shutdown can be either a latched or unlatched input. the output is off whenever shutdow n is low. by simultaneously having shutdown and reset low, the latch is set and shutdown has no effect until reset goes high. the truth table for these inputs is given in table 1. table 1. truth table for the shutdown and reset pins both pins have internal curr ent source pull-ups and should be left disconnected when not in use. an added feature of the current sources is the ability to connect a capacitor and an open-collector driver to the shutdow n or reset pins to provide variable shutdown time. output driver the push-pull driver output has a typical on-resistance of 20 ? . maximum switching times are specified at 75 ns for a 500 pf load. this is sufficient to directly drive mosfets such as the 2n7004, 2n7005, irfd120 and irfd220. larger devices can be driven, but switching times will be longer, resulting in higher switch ing losses. in order to drive large mospower devices, it is necessary to use an external driver ic, such as the vishay siliconix d469a. the d469a can switch very large devices such as the smm20n50 (500 v, 0.3 ? ) in approximately 100 ns. applications vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?70004 . shutdown reset output h h normal operation h normal operation (no change) l h off (not latched) l l off (latched) l off (latched, no change) figure 6. 5 watt power supply for telecom applications si9110 gnd feedback - 48 v 240 k 390 k 13 14 6 10 1 59 2 8 7 4 3 150 k 3 k 100 pf 2n7004 18 k 12 k 1n5822 1n5819 1n4148 v cc 20 f 0.1 f 0.022 f 0.1 f 1 f 220 f 47 f osc sync pulse (if needed) + 5 v at 0.75 a - 5 v at 0.25 a to pin 6 v cc feedback to pin 14 1 1 / 2 w
? all leads 0.101 mm 0.004 e d e b a 1 a h l c 0.25 (gage plane) 1234567 14 13 12 11 10 9 8 package information vishay siliconix document number: 72809 28-jan-04 www.vishay.com 1 soic (narrow): 14-lead (power ic only) millimeters inches dim min max min max a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.38 0.51 0.015 0.020 c 0.18 0.23 0.007 0.009 d 8.55 8.75 0.336 0.344 e 3.8 4.00 0.149 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 l 0.50 0.93 0.020 0.037 ? 0 8 0 8 ecn: s-40080?rev. a, 02-feb-04 dwg: 5914
e 1 e q 1 a l a 1 e 1 b b 1 s c e a d 15 max 1234567 14 13 12 11 10 9 8 package information vishay siliconix document number: 72814 28-jan-04 www.vishay.com 1 pdip: 14-lead (power ic only) millimeters inches dim min max min max a 3.81 5.08 0.150 0.200 a 1 0.38 1.27 0.015 0.050 b 0.38 0.51 0.015 0.020 b 1 0.89 1.65 0.035 0.065 c 0.20 0.30 0.008 0.012 d 17.27 19.30 0.680 0.760 e 7.62 8.26 0.300 0.325 e 1 5.59 7.11 0.220 0.280 e 1 2.29 2.79 0.090 0.110 e a 7.37 7.87 0.290 0.310 l 2.79 3.81 0.110 0.150 q 1 1.27 2.03 0.050 0.080 s 1.02 2.03 0.040 0.080 ecn: s-40081?rev. a, 02-feb-04 dwg: 5919
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